Intel recently announced that it has deployed two of ASML’s latest High-NA Twinscan EXE:5000 EUV lithography machines at its D1 development facility in Hillsboro, Oregon, USA, and has entered the research and development phase. As the world’s first chip manufacturer to receive such equipment, this move signals that Intel is gearing up for its future 14A (1.4nm-class) process node.
According to Intel senior engineer Steve Carson, speaking at the SPIE Advanced Lithography and Patterning Conference, the two machines, installed since 2024, have processed approximately 30,000 wafers to date. While this figure pales in comparison to the throughput of commercial production lines, it is remarkable for a research environment. Each Twinscan EXE:5000 carries a hefty price tag of about 350 million euros, making it an extremely costly investment.
Compared to traditional low-NA EUV lithography tools, High-NA EUV technology offers significant improvements. Low-NA equipment, with its 0.33 numerical aperture (NA) optical system, achieves a single-exposure resolution of around 13.5nm. To reach finer resolutions like 8nm, it typically requires double patterning, which increases production time and costs. In contrast, the Twinscan EXE:5000, equipped with a 0.55 NA lens, can achieve 8nm resolution in a single exposure, shrinking transistor sizes by about 1.7 times and boosting density nearly threefold. This not only simplifies the manufacturing process but also shortens product cycles and improves yield rates. Intel notes that the new equipment demonstrates superior stability compared to earlier models.
However, the advantages of High-NA EUV come at a cost. Its exposure field is reduced to half the size of previous systems, necessitating adjustments in chip design. Moreover, the sheer size and complexity of the equipment are staggering. A single Twinscan EXE:5000 weighs 330,000 pounds, requiring 250 shipping pallets and even three Boeing 747s for delivery. ASML collaborated with German optics giant Zeiss to equip it with an ultra-precise curved mirror system, operating in a vacuum environment, which further drives up manufacturing difficulty and costs.
Intel isn’t simply purchasing the equipment—it’s working closely with ASML to co-optimize the High-NA EUV ecosystem. Technical details, including photomask glass, thin-film materials, and supporting chemicals, are being refined during Intel’s R&D process. This feedback will help ASML enhance its machines and may even contribute to shaping industry standards, giving Intel a competitive edge. By contrast, TSMC has taken a more cautious stance toward High-NA EUV. Its 3nm and below processes currently rely on low-NA equipment with multi-patterning, with plans to gradually adopt similar technology only by 2026.
Though the Twinscan EXE:5000 is positioned as a pre-production tool rather than a mass-production workhorse, Intel is already planning to transition to the more efficient Twinscan EXE:5200 after completing R&D. This follow-up model, expected to begin delivery in 2025, boasts a throughput of up to 220 wafers per hour—sufficient to support the commercial production of the 14A process. Former Intel CEO Pat Gelsinger once stated that High-NA EUV would be a critical step in the company’s bid to reclaim technological leadership in its fierce competition with TSMC and Samsung.
The race to advance semiconductor processes never stops. The introduction of High-NA EUV isn’t just about resolution—it’s a revolution in balancing PPA (performance, power, area). For Intel, being the first to master this technology means simplifying processes and reducing risks at the 1.4nm node and beyond. For the industry as a whole, it may herald the accelerated arrival of the post-3nm era. Currently, Intel is leveraging the Twinscan EXE:5000 to refine its 18A process while paving the way for 14A mass production—a development that undoubtedly warrants close attention.