Today’s high-end computing chips are becoming increasingly large, and TSMC is also doing everything it can to cope. It is now deeply advancing its CoWoS packaging technology, claiming it can create giant chips with an area close to 8000 square millimeters and a power consumption of 1000W, while the performance can be a full 40 times higher than standard processors.
Currently, the maximum interposer area for TSMC’s CoWoS-packaged chips can reach 2831 square millimeters, which is about 3.3 times the reticle limit of TSMC – the maximum reticle size under EUV extreme ultraviolet lithography can reach 858 square millimeters, while TSMC uses 830 square millimeters.
Chips like NVIDIA’s B200 and AMD’s MI300X all use this type of packaging, integrating large computing modules with multiple HBM memory chips.
Next year or slightly later, TSMC will launch its next-generation CoWoS-L packaging technology. The interposer area can reach 4719 square millimeters, about 5.5 times the reticle limit, and it will require a large substrate of 10000 square millimeters (100x100 mm).
It can integrate up to 12 HBM memory chips, including the next-generation HBM4.
That’s not all. TSMC also plans to further increase the interposer area to 7885 square millimeters, about 9.5 times the reticle limit, and will require an 18000 square millimeter substrate. This will allow the packaging of up to 4 computing chips, 12 HBM memory chips, and other IP.
It’s worth noting that this already exceeds the size of a standard CD jewel case (typically 142×125 mm)!
And it’s still not over. TSMC is also continuing research into SoW-X wafer-level packaging technology, which is currently only used by Cerebras and Tesla.
Such giant chips, in addition to requiring complex packaging technology, will also bring challenges of high power consumption and high heat generation. TSMC expects them to reach the 1000W level.
To address this, TSMC plans to directly integrate an entire power management IC on the RDL interposer within the CoWoS-L package. This will shorten the power supply distance, reduce the number of active ICs, lower parasitic resistance, and improve system-level power supply efficiency.
This power management IC will be manufactured using TSMC’s N16 process and TSV (Through-Silicon Via) technology.
For cooling, direct-contact liquid cooling and immersion liquid cooling are essential considerations.
In addition, the size of the OAM 2.0 module form factor is 102×165 mm, and a 100×100 mm substrate is already close to the limit, while 120×150 mm exceeds it. Therefore, the industry needs to jointly develop new OAM form factor standards.
