Intel recently announced significant progress in its 18A process (1.8 nanometer node) and has successfully attracted the attention of several tech giants. According to supply chain sources, Intel has signed a major foundry contract with Microsoft, preparing to use the 18A process to manufacture chips. Meanwhile, companies like Google and Nvidia are in discussions for potential collaborations.
Intel’s 18A process adopts PowerVia backside power delivery technology and RibbonFET gate-all-around transistor architecture, demonstrating significant technological advantages. PowerVia optimizes signal routing and reduces resistance voltage drop by separating the power layer from the signal layer, resulting in an approximately 15% increase in chip performance. Compared to Intel’s 3 process, the 18A process achieves a 30% increase in transistor density, and the SRAM bitcell size is reduced from 0.03 square microns to 0.023 square microns, approaching the density level of TSMC’s N2 process (2 nanometer node). TSMC’s N2 process reaches a transistor density of 313 MTr/mm² on high-density standard cells, higher than 18A’s 238 MTr/mm², but 18A demonstrates lower power consumption and higher frequency potential in high-performance scenarios. Additionally, Intel’s Foveros Direct 3D hybrid bonding technology supports copper-to-copper bump-less connections with a pitch of less than 5 microns, superior to TSMC’s SoIC-X technology’s 4.5 to 9 micron pitch, providing an efficient interconnect solution for AI chips and high-performance computing.
Intel plans to launch the first products based on the 18A process in the second half of 2025, including the Panther Lake processor for AI PCs and Clearwater Forest for servers. Panther Lake supports up to 40 TOPs of AI computing power, and its engineering samples have successfully booted the operating system, with DDR memory performance reaching the target frequency, indicating initial verification of process stability. Clearwater Forest combines RibbonFET, PowerVia, and Foveros Direct 3D technologies to provide high-density, low-power solutions for data centers. Intel has released version 1.0 of its process design kit (PDK) for foundry customers to design chips and plans to achieve mass production in the fourth quarter of 2025, with a full market launch in early 2026. To support production capacity, Intel is accelerating equipment installation at its Fab 52 wafer plant in Arizona, and initial tape-outs will also take place at its Hillsboro, Oregon research and development center.
The current semiconductor industry landscape provides opportunities for Intel. TSMC’s N2 process is expected to enter mass production by the end of 2025, with a monthly capacity of approximately 50,000 wafers. However, due to overwhelming market demand, current capacity is still severely insufficient, forcing customers to look for alternative solutions. Intel’s 18A process, with its performance advantages and domestic US manufacturing capabilities, has attracted customers like Microsoft. Among these major customers, Nvidia has an urgent need for high-performance, low-power processes, while Google’s TPU series could benefit from 18A’s high-density interconnect technology. Broadcom and other companies are also testing the process. In contrast, Samsung’s SF2 process is expected to start trial production in the first quarter of 2025 with a monthly capacity of only 7,000 wafers, and its yield and competitiveness remain to be verified. Intel holds an advantage in technological maturity and customer trust. Furthermore, in 2024, it received a $2.2 billion subsidy from the US CHIPS Act to expand its wafer fabs and research and development.
Intel’s new CEO, Pat Gelsinger, who took office in early 2025, is accelerating the promotion of the foundry business. He emphasizes that the 18A process is key to regaining process leadership and plans to enhance competitiveness through semiconductor design automation, advanced packaging, and foundry services. At the Vision 2025 conference, Gelsinger stated that Intel will prioritize meeting its internal product needs while attracting external customers, with the first external customer tape-outs expected to be completed by mid-2025. He may adjust the “IDM 2.0” strategy to focus on the marketization of the foundry business while deepening cooperation with TSMC to outsource some high-end chips to alleviate initial capacity pressure.
Intel’s 18A process is of significant importance to the AI PC and data center markets. IDC predicts that global AI PC shipments will reach 120 million units in 2025, accounting for 35% of the PC market. If Panther Lake is released on schedule, it will help Intel gain a favorable position in this market. Of course, yield remains a concern, with mass production requiring at least 70% or higher. Intel claims that Panther Lake’s yield is already better than that of Meteor Lake at the same stage, and current process progress is in line with expectations. However, the technical risks associated with high numerical aperture EUV lithography equipment also need attention due to its high cost and process complexity. Therefore, Intel states that it will retain traditional process options to ensure design flexibility.
The breakthrough of Intel’s 18A process injects competitive vitality into the semiconductor industry. With PowerVia, RibbonFET, and Foveros Direct 3D technologies, 18A can compete with TSMC’s N2 process in terms of performance and efficiency. As mass production approaches in 2025, the 18A process will drive upgrades in Intel’s client and server products and may reshape the global foundry market landscape.