According to supply chain sources, AMD plans to launch its next-generation processors based on the Zen 6 architecture by the end of 2026. These Zen 6 chips will leverage both TSMC’s N3 and N2 process nodes, covering product lines across server, desktop, and laptop markets.
Server Segment: EPYC “Venice” Series #
In the server space, AMD’s EPYC “Venice” lineup will consist of two models:
- Venice Classic – targeting general-purpose computing
- Venice Dense – optimized for high-density cloud rack deployments
Both variants will use TSMC’s custom N2P process. Compared to the current N3E node, N2P offers an 8–10% clock speed improvement.
- Venice Classic will integrate 12 Zen 6 cores per chip
- Venice Dense will feature 32 Zen 6c cores per chip
By using an organic interposer for interconnection, eight Venice Dense chips can be combined to form a single processor with up to 256 cores and 512 threads, ideal for hyperscale data center workloads.
Client Segment: Desktop and Laptop Processors #
AMD has multiple offerings planned for the client segment:
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“Olympic Ridge” for desktops:
- Will carry the Ryzen 10000 series
- Built on the N2P node
- Aims to deliver top-tier compute performance
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“Gator Range” for gaming laptops:
- Also based on N2P
- Designed for 55W+ TDP, suitable for high-performance mobile gaming systems
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“Medusa Point” for mainstream thin-and-light laptops:
- Uses a hybrid design
- Compute modules on N2P
- I/O modules on N3P
- Balances performance and power efficiency
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Entry-level models will use a single N3P chip to reduce production costs.
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Roadmap also includes:
- “Medusa Halo” targeting premium devices
- “Bumblebee” for budget markets
- Process node choices for these remain undecided.
Process Node Collaboration with TSMC #
AMD has worked closely with TSMC on process optimizations, including custom metal layers and standard cell libraries. These customizations bring the final chip design closer to a “N2-AMD” stack optimized specifically for AMD, rather than relying solely on the generic N2P node. This co-optimization enhances both chip performance and manufacturing efficiency, while reducing power consumption.
The first Zen 6 chips are expected to be delivered from TSMC fabs before Christmas 2025, with mass production aimed for the 2026 back-to-school laptop market and subsequent server product refreshes.
TSMC N2 vs N3: Technical Advantage #
TSMC’s N2 process offers significant improvements in transistor density and energy efficiency over N3.
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N2 uses 2nm technology and Gate-All-Around FETs (GAA FETs) to reduce transistor size and improve performance
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N3 (3nm) is already widely adopted in high-performance chips
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N2’s introduction is expected to deliver higher clock speeds and lower power consumption, particularly in servers and premium client devices
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N2P is an enhanced version of N2 with better frequency and efficiency
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N3P is a cost- and power-optimized variant of N3, suited for mid-range and budget markets
AMD’s Strategic Market Segmentation #
Zen 6’s diverse designs reflect AMD’s deep understanding of market segmentation.
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In servers:
- Venice Dense’s 256-core architecture addresses the needs of hyperscale data centers
- Venice Classic offers flexible options for traditional enterprise workloads
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In clients:
- Thin-and-light laptops demand longer battery life
- Gaming and creator devices require high compute performance
The Medusa Point series exemplifies this balance with its modular hybrid process design, combining high-performance compute cores with efficient I/O modules.
AMD and TSMC: A Strategic Alliance #
AMD continues to strengthen its position in the processor market through aggressive architectural innovation and close partnership with TSMC. The Zen architecture has enabled AMD to compete fiercely in both performance and market share. TSMC’s leading-edge N3 and N2 process technologies are key enablers for AMD’s roadmap.
Public reports indicate that TSMC plans to enter volume production of N2 in 2025, which aligns well with the Zen 6 release schedule. AMD’s flexible use of both N3 and N2 allows it to optimize cost and performance across diverse market segments.
Ecosystem and Platform Readiness #
The release of the Zen 6 series is also expected to drive broader ecosystem developments:
- Server CPUs in the Venice family will support DDR5, PCIe 5.0, and other next-gen standards, enhancing data center performance
- Ryzen 10000 and mobile processors will support new graphics technologies and display interfaces, catering to gaming, content creation, and everyday productivity
- AMD’s chip designs will also be deeply optimized with OS and software ecosystems, ensuring real-world performance benefits
Summary #
The AMD Zen 6 series, built on a combination of TSMC N2 and N3 processes, represents a highly diversified product strategy:
- Venice targets high-core-count, power-efficient servers
- Ryzen and mobile chips balance performance and cost for consumer markets
This approach showcases AMD’s technical flexibility and lays the foundation for strong competitiveness in the next-generation processor market. With initial deliveries expected by late 2025 and mass production in 2026, AMD is accelerating Zen 6 development to seize the initiative in the upcoming wave of computing innovation.