Sources indicate that AMD will launch its sixth-generation EPYC processors, codenamed “Venice,” in 2026. This new processor will be based on the brand-new Zen 6 and Zen 6C core architectures and will utilize TSMC’s 2nm process technology. The EPYC series targets the data center and high-performance computing (HPC) markets. The Zen 6 architecture will bring generational improvements in core count, cache capacity, and energy efficiency, providing strong support for cloud computing, artificial intelligence, and enterprise-level applications.
As mentioned earlier, the Venice series will offer two core architectures: standard Zen 6 and dense Zen 6C. The Zen 6 core is aimed at high-performance demands, emphasizing single-threaded performance and frequency, while Zen 6C emphasizes multi-core performance, optimizing thread-intensive tasks through higher core density. The flagship model is expected to feature 256 Zen 6C cores and 512 threads, a 33% increase in core count compared to the fifth-generation EPYC Turin (up to 192 Zen 5C cores). The standard Zen 6 model will offer up to 96 cores and 192 threads, comparable to the core count of Turin’s Zen 5 model, but performance and efficiency are expected to improve significantly due to the new architecture and process.
The processors will employ a multi-chip module (MCM) design, containing up to 8 compute chiplets (CCDs), with each CCD integrating 12 Zen 6 cores or more Zen 6C cores. Each CCD will be equipped with 128MB of L3 cache, doubling the maximum 64MB per CCD cache capacity of Turin, resulting in a total cache of up to 1024MB. This design enhances memory access speed, especially suitable for memory-sensitive workloads such as database management and machine learning inference. Zen 6C cores will allocate approximately 2MB of L3 cache per core, optimizing cache efficiency for dense applications, while Zen 6 cores may have a higher per-core cache allocation to support higher frequencies and complex computing tasks.
The Venice series will support the new SP7 and SP8 socket platforms. SP7 is aimed at high-end dual-socket servers, supporting 256 Zen 6C cores with a thermal design power (TDP) of up to 600W, a 50% increase compared to Turin’s 400W, reflecting the higher core density and performance demands. SP8, on the other hand, targets single-socket and entry-level servers, with a core count limit of 128 Zen 6C cores and a TDP between 350-400W, balancing performance and energy efficiency. The SP7 platform supports 16 channels of DDR5 memory, while SP8 supports 12 channels, ensuring high-bandwidth memory access to meet diverse data center needs. Additionally, Venice is expected to support PCIe 5.0 and CXL 2.0, providing faster I/O performance and memory expansion capabilities.
TSMC’s 2nm process (N2) utilizes NanoSheet technology, offering approximately 15% higher performance or 25% lower power consumption compared to the 3nm process, providing Venice with excellent energy efficiency. This process, combined with the Zen 6 architecture, is expected to increase instructions per clock (IPC) by 10-15% in enterprise and cloud workloads, with even greater improvements in HPC and AI tasks depending on optimization. The 2nm process also increases transistor density, supporting higher core integration and smaller die sizes, further reducing production costs.
The Venice series SKUs will cover a wide range of configurations from 8 cores to 256 cores, meeting the diverse needs from edge computing to hyperscale data centers. For example, the flagship EPYC 9006 (Zen 6C) offers 256 cores and 512 threads, suitable for virtualization, containerization, and AI training; mid-range models may offer 64 or 96 cores, optimized for databases and enterprise applications; while low-end models will target telecommunications and embedded systems. AMD will also continue to use the Infinity Fabric interconnect architecture to ensure high-bandwidth, low-latency communication between chiplets and processors, enhancing the scalability of multi-socket systems.
Compared to its predecessors, Venice places a greater emphasis on modularity and flexibility in its architectural design. The 8-CCD layout is a reduction compared to Turin’s maximum of 16 CCDs, but through higher cache capacity and optimized core design, overall performance is expected to increase rather than decrease. AMD may also introduce new branch predictors and instruction prefetch mechanisms to further reduce latency and improve the execution efficiency of complex workloads. In addition, the processor will retain full support for the AVX-512 instruction set, enhancing AI and scientific computing capabilities.
Since its launch in 2017, the AMD EPYC series has seen its market share increase from 2% in 2018 to 34% in 2024, thanks to its high core count, low power consumption, and cost advantages. The release of Venice will further solidify AMD’s competitiveness in the server market, directly competing with Intel’s Xeon series. Intel is expected to launch its Diamond Rapids processors based on the Panther Cove-X architecture this year, with a maximum core count potentially approaching 200, but AMD’s lead in process technology and cache capacity may give it an advantage in energy efficiency and multi-threaded performance.
Venice has currently completed tape-out and entered the production verification phase. AMD’s collaboration with TSMC ensures the mass production stability of the 2nm process, with the first batch of chips being produced at TSMC’s Arizona Fab 21 plant. In the coming months, AMD may announce more SKU details and performance benchmark data, providing data center customers with an upgrade path. The launch of Venice not only marks AMD’s continuous innovation in high-performance computing but will also drive data centers towards higher efficiency and computing density.