Introduction to Ethernet PHY, MAC, and Their Communication Interfaces

Table of Contents

This article introduces the Ethernet MAC (Media Access Control), PHY (Physical Layer), and the standard communication interfaces between them—MII, GMII, SGMII, RMII, and RGMII.

Introduction
#

From a hardware perspective, an Ethernet interface circuit is mainly composed of two parts: the MAC controller and the PHY transceiver. As shown below:

The DMA controller, usually part of the CPU, may also participate in Ethernet data transfers.

In practical designs, these parts are not always separated. Since PHY integrates analog hardware and MAC is purely digital, most systems integrate MAC into microcontrollers, while keeping PHY external. Advanced chip technologies now allow single-chip solutions combining both MAC and PHY. Typical configurations include:

CPU integrating both MAC and PHY (rare)
CPU with integrated MAC and external PHY (common)
CPU without MAC/PHY, using an external MAC+PHY integrated chip (also common)

The MAC and PHY correspond to the Data Link Layer and Physical Layer in the OSI model:

What is MAC?
#

MAC (Media Access Control) is both a hardware controller and a protocol sublayer in the OSI model.

Its responsibilities include:

Controlling access to the physical medium.
Adding headers, addresses, and CRC to frames before sending.
Checking for errors and stripping control information during receive.

MAC hardware looks like this:

MAC frames include destination/source addresses, protocol type, and CRC. To resolve the destination MAC address from an IP address, the ARP protocol is used. The mapping between IP and MAC addresses is stored in the ARP table (viewable on Windows with arp -a).

The MAC chip sits between the PCI bus (host interface) and the PHY (via MII interface):

What is PHY?
#

PHY (Physical Layer Device) is defined in IEEE 802.3. It implements the Physical Layer, managing signal encoding, decoding, and electrical/optical transmission.

The PHY is controlled by the CPU or MAC via the SMI (Serial Management Interface), which reads/writes PHY registers.

Basic PHY structure:

The PHY includes layers such as MII/GMII, PCS (Physical Coding Sublayer), PMA, PMD, and MDI, as standardized in IEEE 802.3.

What is MII?
#

MII (Media Independent Interface) is the standard connection between MAC and PHY, supporting 10/100 Mbps.

It provides:

Data paths (TX/RX)
Status signals
MDIO management interface

The “media independent” design allows any PHY to work with any MAC without redesign.

Relationship with the Reconciliation Sublayer (RS):

MII consists of 16 signals, including TXD, RXD, TX_EN, RX_DV, CRS, COL, TX_ER, RX_ER, MDC, and MDIO.

MII supports 10/100 Mbps operation but uses many pins, making it less practical for high-port-count switches. This led to simplified variants like RMII, SMII, GMII, and RGMII.

What is RMII?
#

RMII (Reduced MII) reduces the pin count by using a 2-bit data bus instead of 4-bit.

For 10 Mbps: MII uses 2.5 MHz clock, RMII uses 5 MHz
For 100 Mbps: MII uses 25 MHz, RMII uses 50 MHz

RMII is widely used in embedded Ethernet devices.

What is GMII?
#

GMII (Gigabit MII) is used for Gigabit Ethernet.

8-bit data bus
125 MHz clock
Supports 10/100/1000 Mbps
Defined in IEEE 802.3-2000

What is RGMII?
#

RGMII (Reduced GMII) simplifies GMII by halving the data lines:

Uses 4-bit TXD/RXD instead of 8-bit
Multiplexes TX_EN/TX_ER into TX_CTL
Operates at 125 MHz for Gigabit Ethernet

What is SMI (MDIO)?
#

SMI (Serial Management Interface), also known as MDIO (Management Data Input/Output), is used for MAC to control PHY registers.

Consists of two signals: MDC (clock) and MDIO (data)
Standardized in IEEE 802.3 Clause 22 (basic) and Clause 45 (extended)
Supports up to 32 PHY devices

FAQ: MAC & PHY in Network Cards
#

Relationship: MAC = Data Link Layer, PHY = Physical Layer. They communicate via MII/GMII and SMI.
Other Components: Network cards also include RJ-45 connectors, transformers (for isolation), EEPROM, BootROM, oscillators, and voltage converters.

Separated MAC/PHY NIC: