As semiconductor technology advances to more sophisticated process nodes, the 2-nanometer (nm) process has become a global focal point in the wafer foundry industry. As the industry leader, TSMC’s progress in its 2nm (N2) process has naturally garnered significant attention. According to supply chain sources, TSMC completed pilot production of its 2nm process by the end of Q1 2025, with yield rates exceeding expectations, laying a solid foundation for mass production by the end of this year. Concurrently, Samsung has also made strides in its 2nm process, though still trailing TSMC.
TSMC’s 2nm process employs Gate-All-Around (GAA) nanosheet transistor technology, which enhances performance and energy efficiency by surrounding the transistor structure on all four sides, a significant improvement over the traditional FinFET architecture. TSMC states that compared to the 3nm (N3) process, the 2nm process offers approximately 15% performance improvement at the same power consumption, a 15% increase in transistor density, and a 25% to 30% reduction in power consumption. Furthermore, the 2nm process shows progress in SRAM density, reaching 38Mb/mm², superior to 3nm’s 33.55Mb/mm². These enhancements are highly valuable for high-performance computing (HPC) and smartphone SoCs.
In terms of yield rates, TSMC’s 2nm pilot production performance has been particularly impressive. In early 2025, industry sources reported that the pilot production line at TSMC’s Hsinchu Baoshan factory (Fab 20) had achieved yield rates exceeding 90%, far surpassing the 70% to 80% threshold required for mass production. While this data originated from memory products, it indirectly reflects TSMC’s profound accumulation in process optimization. To support mass production, TSMC has increased equipment investment, ordering 30 ASML EUV lithography machines in 2024 and planning to purchase another 35 in 2025, including cutting-edge High-NA EUV lithography machines. This equipment will help TSMC achieve large-scale production of 2nm chips in the second half of 2025, with an initial estimated monthly capacity of 50,000 wafers by year-end, further increasing to 120,000 to 130,000 wafers by 2026.
TSMC’s 2nm process has attracted the attention of numerous industry giants. Apple Inc. is expected to be among the first customers to adopt this process, with its next-generation M5 chips and A19 Pro chips slated for future Mac, iPad, and iPhone 17 series devices, respectively. Companies like NVIDIA, AMD, and Qualcomm are also actively vying for production capacity to meet the demands of the AI and high-performance computing markets. To address market demand, TSMC is accelerating factory expansion; its Kaohsiung wafer fab (Fab 22), originally planned for two 2nm factories, is now considering the addition of a third.
In contrast, Samsung’s progress in the 2nm process appears to be slightly behind. Samsung also employs GAA technology and plans to mass produce its first 2nm chip, the Exynos 2600, in November 2025, targeting its integration into the Galaxy S26 series, slated for release in 2026. Korean media reports indicate that Samsung’s 2nm pilot production yield rates have improved from 20% to 30% earlier this year to 40% to 50%, still a significant gap compared to TSMC. Samsung is attempting to attract more customers by optimizing production lines and adjusting operational strategies. However, this market often sees a winner-take-all scenario, with market share data showing TSMC holding 67.1% of the global wafer foundry market in Q4 2024, while Samsung accounted for only 8.1%.
Intel is also actively positioning itself in the 2nm race, with its 18A process (equivalent to 2nm class) also set for mass production in 2025, and its main product, Clearwater Forest, has completed design. Intel utilizes RibbonFET transistors and PowerVia (backside power delivery) technology. Although Intel’s share in the foundry market is low, at only about 1%, its technology roadmap shows some competitiveness. Additionally, the emerging Japanese foundry Rapidus plans to commence 2nm pilot production in April 2025, targeting mass production in 2027, but its technology relies heavily on IBM, making it unlikely to significantly impact the market landscape in the short term.
While the mass production of the 2nm process is an absolute technological advancement, it also brings increased costs. The foundry price for TSMC’s 2nm wafers is currently about $30,000 per wafer, approximately 10% higher than 3nm. The high cost stems from investments in advanced equipment and increased process complexity. In the future, TSMC also plans to introduce the 1.4nm (A14) process, expected to enter mass production in 2028, at which point wafer prices could reach $45,000.
From an industry trend perspective, the commercialization of the 2nm process will further solidify TSMC’s market dominance. The surge in demand for generative AI and high-performance computing has made advanced processes central to wafer foundry competition. TSMC, with its stable yield rates, broad customer base, and strong capacity planning, continues to lead in the 2nm era. While Samsung and Intel are actively catching up technologically, they are unlikely to unseat TSMC’s leadership position in the short term. Moving forward, as process technology approaches physical limits, wafer foundries will need to balance cost control, technological innovation, and customer collaboration to maintain their competitive advantage.
TSMC’s breakthrough in the 2nm process sets a new benchmark for the semiconductor industry. Its high yield rates, excellent performance, and clear mass production plan not only meet the demands of the AI and high-performance computing markets but also provide technical support for the iteration of consumer electronics like smartphones.