Recently, AMD held its Advancing AI 2025 conference in San Jose, California. Dr. Lisa Su, the company’s CEO, unveiled the latest development roadmap for its data center product line, confirming that the EPYC Venice processor, based on the Zen 6 architecture, will be launched in 2026 with up to 256 cores. Furthermore, the EPYC Verano processor based on the Zen 7 architecture and the Instinct MI500 series accelerators are planned for release in 2027.
EPYC Venice: The Next Generation of Server CPUs #
The EPYC Venice processor is the core product of AMD’s sixth-generation EPYC series, featuring the new Zen 6 microarchitecture, and is currently slated for release in H2 2026. This processor will be available in two variants: a standard Zen 6 version and a higher core-density Zen 6c version. The standard version will support up to 96 cores and 192 threads, with a maximum of 8 CCDs, while the Zen 6c version will extend the core count to 256 cores, supporting 512 threads, also utilizing up to 8 CCD designs. Compared to the fifth-generation EPYC Turin (Zen 5c version with up to 192 cores, 384 threads, and 12 CCDs), Venice achieves an improvement in core density and thread processing capability. This design continues AMD’s consistent multi-core strategy, targeting cloud computing, high-performance computing (HPC), and large-scale data analytics scenarios.
The Venice processor will be manufactured using TSMC’s 2-nanometer process. Compared to the 3-nanometer and 4-nanometer processes used for the fifth-generation EPYC, the 2-nanometer process further optimizes transistor density and power efficiency. AMD states that Venice’s memory bandwidth will reach 1.6 TB/s, a significant increase from the existing products’ 614 GB/s, expected to be achieved through support for 16-channel or 12-channel DDR5 memory and emerging MR-DIMM or MCR-DIMM technologies. Furthermore, the bandwidth between the processor and GPU will double, utilizing a PCIe 6.0 interface capable of 128 GB/s bi-directional data transfer rate (excluding encoding overhead). With the backing of 128 PCIe lanes, data throughput capability will be greatly enhanced, meeting the demands of high-bandwidth applications such as AI training and inference. AMD also revealed that Venice’s overall performance is approximately 70% higher than its predecessor, thanks to architectural optimizations, process advancements, and higher core density.
EPYC Venice will support the new SP7 and SP8 sockets, with SP7 targeting the high-end server market, supporting higher power and more features, while SP8 is designed for entry-level servers, offering a more economical solution. In terms of power consumption, Venice is expected to exceed the existing SP5 socket’s peak power limit of 700W, potentially approaching or exceeding 1000W. To address the thermal challenges posed by high power consumption, AMD may introduce advanced cooling technologies to ensure system stability.
Instinct MI400 Series and Helios Platform #
Also launching concurrently with EPYC Venice is the Instinct MI400 series accelerator, planned for release in 2026. This series will offer up to 40 PFLOPs of computing power, representing a 10x performance increase compared to the current MI350 series. The MI400 will be equipped with 432 GB of HBM4 memory and a bandwidth of 19.6 TB/s, making it the first GPU accelerator to adopt HBM4, significantly surpassing existing HBM3 solutions. HBM4’s high bandwidth and low latency characteristics make it particularly suitable for processing ultra-large language models and generative AI workloads. AMD plans to integrate EPYC Venice, Instinct MI400, and Vulcano FPGA into the Helios data center rack, forming a unified AI and high-performance computing platform to further enhance system-level performance and scalability.
Looking to 2027: EPYC Verano and Instinct MI500 #
Looking ahead to 2027, AMD will introduce the EPYC Verano processor and the Instinct MI500 series accelerators. EPYC Verano is expected to be based on the Zen 7 architecture, which is anticipated to achieve further breakthroughs in instruction sets, cache design, and power efficiency ratio. The specific specifications of the Instinct MI500 series are currently unknown, but AMD states that it will bring massive improvements in AI inference performance, targeting the next generation of AI rack systems. The MI500 may utilize TSMC’s more advanced A16 process (expected to enter mass production in late 2026) and support backside power delivery technology to optimize power consumption and performance.
AMD’s roadmap reflects the data center industry’s trend towards higher core density, stronger computing capabilities, and more efficient memory bandwidth. With the explosive growth of AI workloads, server processors need to handle larger-scale parallel computing tasks, with high-bandwidth memory and high-speed interconnect technologies becoming critical. The combination of EPYC Venice and MI400 will provide powerful support for cloud computing, scientific computing, and AI training in 2026, while Verano and MI500 will further push the boundaries of technology in 2027.
Competitive Landscape and Strategic Integration #
From a competitive standpoint, AMD’s 256-core EPYC Venice will directly challenge Intel’s next-generation Xeon processors, such as Diamond Rapids and Clearwater Forest, which are also expected to offer high core counts and utilize advanced process technology. Intel’s Xeon series has been gradually surpassed by AMD in multi-core performance in recent years, with EPYC Genoa (Zen 4, 96 cores) already demonstrating up to 4 times the performance of the Xeon Platinum 8380. The launch of Venice will further widen this gap, especially in the cloud service provider and hyperscale data center markets. On the other hand, ARM-based processors (such as Amazon Graviton 3) have emerged with low-power advantages in certain scenarios, but their performance is still hard to match the dominance of x86 architecture in high-performance computing. AMD, by continuously increasing core counts and bandwidth, has consolidated its leading position in the x86 server market.
AMD’s Helios platform integrates processors, accelerators, and network interface cards (such as the Vulcano 800 GbE NIC), demonstrating its strategy of building end-to-end data center solutions. The Vulcano NIC supports the UEC 1.0 specification, providing up to 800 Gbps of network bandwidth, which can effectively reduce data transfer bottlenecks and enhance the overall efficiency of rack-level systems. This full-stack design enables AMD to optimize the synergy between hardware components, offering customers higher performance and lower total cost of ownership.
From a technical detail perspective, the Zen 6 architecture is expected to innovate in cache design, potentially including a larger L3 cache (up to 128 MB per CCD) and redesigned L2 cache to reduce latency and improve multi-threading performance. Additionally, AMD may introduce more advanced chip interconnect technologies in Venice, such as TSMC’s CoWoS-S or InFO_LSI, to support faster communication between more chips. This will contribute to efficient synergy at high core counts, especially in multi-chip module (MCM) designs.
AMD’s EPYC Venice, Verano, and Instinct MI400, MI500 series demonstrate its long-term planning in the data center market. By adopting cutting-edge processes, increasing core density, and optimizing bandwidth, AMD not only meets the current needs of AI and high-performance computing but also lays the foundation for technological evolution in the coming years. Venice and MI400 in 2026 will bring a performance leap to data centers, while Verano and MI500 in 2027 will further push the boundaries of AI and cloud computing. These products will undoubtedly attract widespread attention from tech enthusiasts and industry users.