In its pursuit of highly integrated, large-scale chip solutions, Arm is revealing its design blueprint to capitalize on the opportunities within the semiconductor industry. To ensure its computing building blocks, including CPU chiplets and custom application-specific chiplets, are a part of the multi-die silicon platform, Arm is forming strategic partnerships with chip design companies and semiconductor IP vendors.
Furthermore, Arm is actively involved in standardization efforts to create a common design framework for chiplets. This is significant as Arm’s AMBA specifications have been a cornerstone of SoC connectivity for over two decades.
Arm’s Chiplet Blueprint #
What is Arm doing in the design and development of highly integrated large-scale chip solutions? The IP giant is gradually unveiling its design blueprint to meet one of the most exciting opportunities in today’s semiconductor industry.
It is crucial for Arm to ensure its computing building blocks have a place on multi-die silicon platforms, whether they are CPU chiplets or customized application-specific chiplets. Therefore, Arm is building strategic partnerships with chip design companies and semiconductor IP vendors to ensure Arm-based systems are part of the chiplet revolution.
Arm is also actively involved in standardization efforts to define a common design framework for chiplet design. This is important because for over 20 years, Arm’s AMBA specifications have formed the cornerstone of SoC connectivity design.
Alphawave Semi Alliance #
Arm’s partnership with chip IP vendor Alphawave Semi provides some clues to the Cambridge, UK-based company’s larger blueprint for multi-die silicon devices. In October 2023, Alphawave Semi joined the Arm Total Design program to create chiplet solutions based on the Arm Neoverse Compute Subsystem (CSS).
Alphawave Semi will integrate Arm Neoverse CSS compute with custom chips and pre-built chiplets that support Universal Chiplet Express (UCIe). Its UCIe IP will support Arm fabric interfaces, such as AXI and CHI interfaces, making it easy to integrate connectivity for interfaces like CXL, HBMx, DDRx, and Ethernet into custom Arm-based SoCs and chiplets.
In short, Alphawave Semi is combining its high-speed connectivity IP and chiplet platform with Arm’s Neoverse CSS reference IP solution. Additionally, its professional team will enhance and optimize the Power, Performance, and Area (PPA) of Neoverse cores for key process nodes, scaling down to 3nm and 2nm processes.
In June 2024, Alphawave Semi announced the development of an advanced compute chiplet based on the Arm Neoverse CSS platform for Artificial Intelligence (AI) and Machine Learning (ML), High-Performance Computing (HPC), data center, and 5G/6G network infrastructure applications. This collaboration adds significant differentiation to Alphawave Semi’s design platform, including I/O expansion chiplets, memory chiplets, and compute chiplets.
Arm also partnered with Japanese design company Socionext to develop a 32-core CPU chiplet on TSMC’s 2nm process node. This CPU chiplet, built around the Arm Neoverse CSS platform, is designed for single or multiple instantiations within a single package. It also includes I/O and application-specific custom chiplets to optimize performance for various applications.
Arm’s Chiplet Blueprint #
Richard Grisenthwaite, Arm’s Executive VP, Chief Architect, and Fellow, recently provided some clues about the company’s chiplet design blueprint in a blog post. First, it has initiated the Arm Chip System Architecture (CSA) program to enable greater reuse of components like PHY and soft IP across multiple vendors.
The program, which consists of more than 20 partners, is analyzing and defining the best partitioning options for chiplet-based systems. It is also exploring new ways to better standardize system design choices for different types of chiplets.
Next, Arm is updating its AMBA specifications for on-die and off-die interfaces for chiplet designs. Arm’s AMBA specifications, such as AXI and CHI, are already used in billions of semiconductor devices.
Arm is also actively involved in creating industry standards, such as UCIe, which defines the physical layer (PHY) for transferring data between chiplets within a package. In addition to bringing SoC interconnect protocols like AMBA to chiplet designs, Arm is committed to adopting industry standards like PCIe and CXL to aggregate well-defined peripherals from a motherboard into a single package.
Finally, as part of a concerted effort to create many non-differentiated options in chiplet partitioning, Arm is exploring the decomposition of SoCs into chiplets for Arm-based systems using the AMBA protocol. These initiatives aim to accelerate the design process for chiplet-based systems.
Chiplet Partitioning Framework #
Arm’s investment in the AMBA and CSA areas shows that it is trying to decompose Arm-based systems into multiple chiplets. This is crucial because reusability can create interesting new possibilities for the burgeoning chip market. The partnerships with connectivity IP experts, like Alphawave Semi, appear to be part of an effort to simplify chiplet partitioning.
Nevertheless, the standards for a common framework will play a crucial role in creating viable chiplet solutions, which is why Arm is actively involved in UCIe and other standardization efforts. Its own CSA initiative aims to build a consensus around the most valuable partitioning schemes to reduce fragmentation.